Many current computer system designs use data processors capable of performing page-mode memory access cycles. Commercial integrated circuit dynamic random access memories (DRAMs) must be able to perform the page-mode cycles. In a traditional DRAM access cycle, a row address is provided to the DRAM. A signal known as "RAS" becomes active to indicate that a valid row address is present. The DRAM then performs row decoding and activates a word line in response to the row address. Each memory cell coupled to the word line then provides its contents to a corresponding differential bit line pair. Then, a second address known as a column address becomes valid and a signal known as "CAS" indicates that a valid column address is present. The column address is used to select one bit line, and the data represented as a differential voltage on the selected bit line is subsequently provided externally. Each successive cycle includes row decoding followed by column decoding. In page mode, however, after the row address selects a word line, the column address alone is provided in two or more subsequent cycles. Page mode improves system performance by saving the DRAM from the task of repeatedly performing row decoding to select the same word line. Page mode is useful because data stored in the memory is likely to be accessed from adjacent memory addresses. Thus it is advantageous to design DRAMs to maximize performance during page mode.